The present invention relates to a semiconductor device, including metal interconnects laid in an insulating film with a low dielectric constant (which will be herein called a low-dielectric-constant film), and also relates to a method for fabricating the same.
Hereinafter, the structure of a semiconductor device, including inlaid metal interconnects in a low-dielectric-constant film, will be described with reference to FIG. 6.
As shown in FIG. 6, a second insulating film 102 is formed of a silicon dioxide film, for example, on a first insulating film 101 deposited on a semiconductor substrate 100. In the second insulating film 102, metal interconnects 105 have been formed. Specifically, each of the metal interconnects 105 consists of a barrier metal layer 105a of tantalum nitride, for example, and a main interconnect layer 105b of copper, for instance.
In this semiconductor device, the second insulting film 102, which exists between the metal interconnects 105, is made of silicon dioxide with a dielectric constant between about 3.9 and about 4.2. Therefore, a parasitic capacitance, generated between the metal interconnects 105, increases, thereby interfering with high-speed operation of the semiconductor device.
To solve this problem, a carbon-containing silicon dioxide film with a low dielectric constant of about 2.5 may be used as the second insulating film 102.
Hereinafter, a method for fabricating a semiconductor device, including inlaid metal interconnects formed in an insulating film of carbon-containing silicon dioxide, will be described with reference to FIG. 7A through FIG. 7E.
First, as shown in FIG. 7A, a second insulating film 110 of carbon-containing silicon dioxide, is deposited on a first insulating film 101 formed on a semiconductor substrate 100. Then, a resist pattern 111 with openings for forming interconnect grooves is defined on the second insulating film 110 as shown in FIG. 7B.
Next, as shown in FIG. 7C, the second insulating film 110 is plasma-etched using an etching gas, consisting essentially of fluorine and carbon, and being masked with the resist pattern 111. In this manner, interconnect grooves 112 are formed in the second insulating film 110. As a result, the upper part of the resist pattern 111 changes into a cured layer 111a. Specifically, the bonding states of atoms in the cured layer 111a are different from those of atoms in the original material of the resist pattern 111 that has not yet been plasma-etched. And the cured layer 111a is made of a polymer consisting essentially of fluorine and carbon and has a thickness of about 50 nm. The cured layer 111a cannot be removed by a wet etching process but can be removed by a plasma etching process using oxygen gas.
Accordingly, the resist pattern 111 is ashed away with oxygen plasma as shown in FIG. 7D. In this case, the ashing process is performed by a down flow technique (in which no bias voltage is applied to the substrate) in a vacuum between about 267 Pa and about 400 Pa, for example, and with the substrate heated to a relatively high temperature between about 150xc2x0 C. and about 250xc2x0 C., for instance. In this manner, the resist pattern 111 with the cured layer 111a in its upper part can be stripped just as intended. Also, a silicon dioxide film 113 with a thickness of 200 nm, for example, is formed in the upper part of the second insulating film 110 of carbon-containing silicon dioxide.
In the ashing process using oxygen plasma, carbon is removed from the carbon-containing silicon dioxide for the second insulating film 110, thereby producing silicon dioxide. Hereinafter, this mechanism will be described with reference to FIGS. 8 and 9.
FIG. 8 illustrates an example of a chemical formula representing a carbon-containing silicon dioxide. If the carbon-containing silicon dioxide represented by this chemical formula and oxygen are bonded together, the following chemical reaction
2CH3+7Oxe2x86x922CO2↑+3H2O↑
occurs. Then, CH3, which has been bonded to Si, disappears. That CH3 disappeared is replaced with O to form SiO2 bonds. Therefore, a silicon dioxide as represented by the chemical formula shown in FIG. 9 is produced.
Next, a tantalum nitride film is deposited over the second insulating film 110, or on the silicon dioxide film 113 more exactly, by a sputtering process. And then, a copper film is deposited on the tantalum nitride film by an electro-plating process. Thereafter, excessive parts of the copper and tantalum nitride films, existing over the second insulating film 110, are removed by a CMP process, thereby defining metal interconnects 114 as shown in FIG. 7E. The metal interconnects 114 are made up of a barrier metal layer 114a of tantalum nitride and a main interconnect layer 114b of copper.
However, the semiconductor device formed in this manner has the following problems.
First of all, in the step of ashing away the resist pattern 111 using oxygen plasma, the silicon dioxide film 113 is adversely formed in the upper part of the second insulating film 110 of carbon-containing silicon dioxide. Specifically, the silicon dioxide film 113 exhibits a high dielectric constant and has a thickness of 200 nm, for example. Therefore, although the carbon-containing silicon dioxide film is used as the second insulating film 110, a parasitic capacitance generated between the metal interconnects 114 cannot be reduced sufficiently.
Also, the silicon dioxide film 113 has a density between 1.7 g/cm3and 1.8 g/cm3, which is lower than that of a silicon dioxide film formed by a plasma CVD process, for instance. Therefore, when oxygen plasma is supplied in a subsequent process step, oxygen ions go through the silicon dioxide film 113 to reach and oxidize the carbon-containing silicon dioxide film under the film 113. As a result, the silicon dioxide film 113 has its film thickness increased undesirably. This phenomenon is observed, for example, in the subsequent process step of ashing away a resist pattern for forming via holes over the metal interconnects 114. The phenomenon is also observed, for instance, in the subsequent process step of ashing away a resist pattern for forming interconnect grooves for upper-level metal interconnects to be formed over the via holes.
As described above, in the known semiconductor device including inlaid metal interconnects in an insulating film of carbon-containing silicon dioxide, a thick silicon dioxide film is unintentionally formed in upper parts of the insulting film that surround the metal interconnects. As a result, a parasitic capacitance generated between the metal interconnects increases disadvantageously.
It is therefore an object of the present invention to enhance the performance of a semiconductor device, including inlaid metal interconnects in an insulating film of carbon-containing silicon dioxide, by reducing a parasitic capacitance produced between the metal interconnects.
To achieve this object, a first inventive semiconductor device includes: an insulating film formed of a carbon-containing silicon dioxide film on a substrate; an interconnect groove formed in the insulating film; a silicon dioxide layer, which is formed on the bottom and side faces of the interconnect groove and has a density high enough to allow almost no oxygen to pass therethrough; and a metal interconnect formed on the silicon dioxide layer inside the interconnect groove.
In the first inventive device, the silicon dioxide layer with a density high enough to allow almost no oxygen to pass therethrough is formed on the bottom and side faces of the interconnect groove. Therefore, even if oxygen plasma is supplied in a subsequent process step, oxygen ions cannot pass through the silicon dioxide layer, and the carbon-containing silicon dioxide film surrounding the silicon dioxide layer is not oxidized. Accordingly, the thickness of the silicon dioxide layer, existing on the bottom and side faces of the interconnect groove, does not increase. As a result, a parasitic capacitance produced between the metal interconnects can be reduced just as intended.
In one embodiment of the first device, the silicon dioxide layer preferably has a density of 2.0 g/cm3 or more.
In such an embodiment, the silicon dioxide layer prevents the oxygen ions from passing therethrough with much more certainty. As a result, it is possible to suppress the increase in thickness of the silicon dioxide layer existing on the bottom and side faces of the interconnect groove.
A second inventive semiconductor device includes: an insulating film formed of a carbon-containing silicon dioxide film on a substrate; an interconnect groove formed in the insulating film; a silicon dioxide layer, which is formed on the bottom and side faces of the interconnect groove and has a small and uniform thickness; and a metal interconnect formed on the silicon dioxide layer inside the interconnect groove.
In the second inventive device, the silicon dioxide layer with a small and uniform thickness is formed on the bottom and side faces of the interconnect groove. In other words, the silicon dioxide layer, existing between the metal interconnects, has a high dielectric constant and a small and uniform thickness. As a result, a parasitic capacitance produced between the metal interconnects can be reduced just as intended.
In one embodiment of the second device, the silicon dioxide layer preferably has a thickness of 20 nm or less.
In such an embodiment, the parasitic capacitance produced between the metal interconnects can be further reduced.
A first inventive method for fabricating a semiconductor device includes the steps of: a) forming an insulating film of a carbon-containing silicon dioxide film on a substrate; b) etching the insulating film using a resist pattern as a mask, thereby forming an interconnect groove in the insulating film; c) performing a dry etching process using an etching gas containing oxygen, thereby removing a cured layer and forming a silicon dioxide layer on the bottom and side faces of the interconnect groove; d) removing the resist pattern by a wet etching process; and e) filling the interconnect groove with a metal film to form a metal interconnect. The cured layer has been formed in an upper part of the resist pattern as a result of the step b).
According to the first inventive method, by performing a dry etching process using an etching gas containing oxygen, a cured layer, formed in an upper part of a resist pattern as a result of the step b), is removed and a silicon dioxide layer is formed on the bottom and side faces of an interconnect groove. Therefore, the bottom and side faces of the interconnect groove are exposed to the etching gas containing oxygen for just a short time. Accordingly, a silicon dioxide layer with a small and uniform thickness is formed on the bottom and side faces of the interconnect groove. Also, the resist pattern having the cured layer removed is stripped by a wet etching process. Therefore, in the step d), the bottom and side faces of the interconnect groove are not exposed to the oxygen plasma, and the thickness of the silicon dioxide layer does not increase. Consequently, it is possible to reduce a parasitic capacitance produced between the metal interconnects just as intended.
In one embodiment of the first method, the dry etching process is preferably performed within a plasma ambient at a pressure of 13.3 Pa or less.
Then, a silicon dioxide layer with a thickness of about 20 nm or less can be formed on the bottom and side faces of the interconnect groove. As a result, the parasitic capacitance produced between the metal interconnects can be further reduced.
In this particular embodiment, the dry etching process is preferably an anisotropic RIE process.
In such an embodiment, a silicon dioxide layer with a thickness of about 20 nm or less and a density high enough to allow almost no oxygen to pass therethrough can be formed on the bottom and side faces of the interconnect groove. Therefore, even if oxygen plasma is supplied in a subsequent process step, oxygen ions cannot pass through the silicon dioxide layer, and a carbon-containing silicon dioxide film surrounding the silicon dioxide layer is not oxidized. Accordingly, the thickness of the silicon dioxide layer, existing on the bottom and side faces of the interconnect groove, does not increase. As a result, the parasitic capacitance produced between the metal interconnects can be reduced just as intended.
In another embodiment, the first inventive method preferably further includes the step of removing the silicon dioxide layer, existing on the bottom and side faces of the interconnect groove, by a wet etching process.
In such an embodiment, the silicon dioxide layer with a high dielectric constant no longer exists between the metal interconnects. As a result, the parasitic capacitance produced between the metal interconnects can be further reduced.
A second inventive method for fabricating a semiconductor device includes the steps of: a) forming an insulating film of a carbon-containing silicon dioxide film on a substrate; b) etching the insulating film using a resist pattern as a mask, thereby forming an interconnect groove in the insulating film; c) filling the interconnect groove with a resist film; d) removing a part of the resist film, existing over the interconnect groove, and the resist pattern with a cured layer by a dry etching process using an etching gas containing oxygen; e) removing the other part of the resist film, still existing inside the interconnect groove, by a wet etching process; and f) filling the interconnect groove with a metal film to form a metal interconnect. The cured layer has been formed in an upper part of the resist pattern as a result of the step b).
In the second inventive method, an interconnect groove is filled with a resist film and then a cured layer, existing in an upper part of a resist pattern, is removed by a dry etching process using an etching gas containing oxygen. Therefore, the bottom and side faces of the interconnect groove are not exposed to the etching gas containing oxygen, and no silicon dioxide layer is formed thereon. The other part of the resist film, still existing in the interconnect groove, is removed by a wet etching process. Accordingly, the bottom and side faces of the interconnect groove are not exposed to the oxygen plasma, and no silicon dioxide layer is formed thereon in the step e). As a result, a parasitic capacitance produced between the metal interconnects can be reduced just as intended.
In one embodiment, the second inventive method preferably further includes the step of performing an anisotropic RIE process between the steps e) and f) within a plasma ambient containing oxygen at a pressure of 13.3 Pa or less to form a silicon dioxide layer on the bottom and side faces of the interconnect groove.
In such an embodiment, it is possible to form a silicon dioxide layer with a thickness of about 20 nm or less and a density high enough to allow almost no oxygen to pass therethrough on the bottom and side faces of the interconnect groove. Therefore, even if oxygen plasma is supplied in a subsequent process step, oxygen ions cannot pass through the silicon dioxide layer, and a carbon-containing silicon dioxide film surrounding the silicon dioxide layer is not oxidized. As a result, the parasitic capacitance produced between the metal interconnects can be reduced just as intended.